Interrupts are commonly used in computer systems to provide a mechanism to force software to alter its current execution and perform tasks that “service” the interrupt. For example, if there is incoming valid data on a serial data interface which is to be stored in a buffer, the serial data interface may assert an interrupt which, when serviced, causes the data to be captured and placed in the buffer. In many cases, the prioritization of the serving of interrupts is important as many interrupts relate to interrupt sources that have a limited tolerance for the latency associated with servicing of interrupts. For example, the data on the serial data interface may only be valid for a limited amount of time, thus requiring it to be captured within that time period. Servicing of interrupts is typically accomplished through the use of software routines commonly referred to as interrupt service routines or interrupt handlers.
A typical prior art interrupt controller module receives interrupt requests from multiple interrupt sources. The requests are stored in an interrupt source register having a bit corresponding to each of the interrupt sources such that the interrupt source register can be read to determine which sources are asserting pending interrupts. An interrupt enable register stores a bit corresponding to each of the potential pending interrupts such that individual bit masking of the interrupt source register is facilitated. A logical AND is performed on the interrupt source register and the content of the interrupt enable register in order to form the content of an interrupt pending register. Thus, if an interrupt is asserted and is enabled by the mask register, a logical one will be generated for that interrupt in the interrupt pending register. A logical bit-wise OR is performed on the interrupt pending register in order to generate an interrupt signal that is routed to the central processing unit (CPU). As such, any pending interrupts which are enabled will force assertion of the interrupt signal to the CPU.
When the CPU detects that the interrupt signal has been asserted, the interrupt pending register can be examined to determine which interrupt service routine should be executed in response. This may involve resolving interrupt prioritization, where the prioritization may be based on the bit location of a particular interrupt in the interrupt pending register. Thus, the more significant bits in the interrupt pending register may have higher priority than less significant bits. Because the interrupt source register and interrupt pending registers are read-only, such prior art interrupt controllers are limited in that software interrupt requests can only be generated by forcing hardware to assert an interrupt request.
Another prior art interrupt controller is described in U.S. Pat. No. 5,459,872 issued to Connell et al. (hereinafter “Connell”). Connell describes an interrupt controller that includes an interrupt register that stores pending interrupts corresponding to a plurality of hardware interrupt sources. Control software is also included which can cause interrupt requests to be asserted by modifying the interrupt register. Although the teachings of Connell allow software interrupts to be generated by modifying the hardware interrupt indications stored in the interrupt register, there is no way to distinguish between hardware and software generated interrupts by referencing the contents of the interrupt register. In addition, the number of different interrupt requests supportable by the interrupt controller as taught by Connell is limited to the number of hardware interrupt sources supported by the interrupt register.
Therefore, a need exists for an interrupt controller that allows hardware and software interrupts to be distinguished while providing for unified processing of both hardware and software interrupt requests.
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